阳明交通大学 电信工程研究所

 

Ø      VLSI technology

[16] R.Shirota, Y.Itoh, R.Nakayama, M.Momodomi, S.Inoue, R.Kirisawa, Y.Iwata, M.Chiba, and F.Masuoka, “A new NAND cell for ultra high density 5V only EEPROMs,” in Symp. VLSI Technology Dig. Tech. Papers, pp.33-34, June 1988.

[17] R.Kirisawa, S.Aritome, R.Nakayama, T.Endoh, R.Shirota, and F.Masuoka, "A NAND Structured Cell with a New Programming Technology for High Reliable 5 V-Only Flash EEPROM," in Symp. VLSI Technology Dig. Tech. Papers, pp.129-130, June 1990.

[18] H.Watanabe, S.Aritome, G.J.Hemink, T.Maruyama, R.Shirota, “Sacling of tunnel oxide thickness for Flash EEPROMs Realizing Stress-Induced Leakage Current Reduction”, in Symp. VLSI Technology Dig. Tech. Papers, pp.47-45, June, 1994.

[19] H.G.Hemink, T.Tanaka, T.Endoh, S.Aritome, and R.Shirota, “Fast and accurate programming method for multilevel NAND flash EEPROM’s,” in Symp. VLSI Technology Dig. Tech. Papers, pp.129-130, June 1995.

[20] S.Satoh, K.Shimizu, T.Tanaka, F.Arai, S.Aritome, and R.Shirota, “A novel Channel Boost Capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4Gbit NAND Flash memories,” in Symp. VLSI Technologies Dig. Tech. Papers, pp.108-109, June 1998.

[21] M.Ichige, Y.Takeuchi, K.Sugimae, A.Sato, M.Matsui, T.Kamigaki, H.Kutsukake, Y.Ishibashi, M.Saito, S.Mori, H.Meguro, S.Miyazaki, T.Miwa, S.Takahashi, T.Iguchi, N.Kawai, S.Tamon, N.Arai, H.Kamata, T.Minami, H.Iizuka, M.Higashitani, T.Pham, G.Hemink, M.Momodomi and R.Shirota, “A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND Flash EEPROMs,” in Symp. VLSI technologies Dig. Tech. Papers, pp.89-90, June 2003.

 

Ø      VLSI Circuits

[22] T.Tanaka, M.Momodomi, Y.Iwata, Y.Tanaka, H.Oodaira, Y.Itoh, R.Shirota, K.Ohuchi, and F.Masuoka, “A 4-Mbit NAND-EEPROM with tight programmed Vt distribution,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.105-106, June 1990.

[23] T.Tanaka, Y.Tanaka, H.Nakamura, H.Oodaira, S.Aritome, R.Shirota, and F.Masuoka, “A Quick Intelligent Page-Programming Architecture 3V-Only NAND- EEPROMs,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.20-21, June 1992.

[24] T.Tanzawa, T.Tanaka, K.Takeuchi, R.Shirota, S.Aritome, H.Watanabe, G.Hemink, K.Shimizu, S.Sato, Y.Takeuchi, and K.Ohuchi, “A compact on-chip ECC for low cost Flash memories,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.59-60, June 1996.

 

Ø      Other Conferences

[25] M.Momodomi, Y.Iwata, T.Tanaka, Y.Ithoh, R.Shirota, F.Masuoka, “A high density NAND EEPROM with Block-page Programming for Micorcomputer Applications”, in IEEE CICC, pp.10.1.1-4, May, 1989.

 

[26] S.Aritome, R.Kirisawa, T.Endoh, N.Nakayama, R.Shirota, K.Sakui, K.Ohuchi, and F.Masuoka, “Extended Data Retention Characteristics after more than 104 Write and Erase Cycles in EEPROM’s,” in IEEE IRPS 1990, pp.259-264, 1990.

[27] S.Aritome, K.Hatakeyama, T.Endoh, T.Yamaguchi, S.Shuto, H.Iizuka, T.Maruyama, H.Watanabe, G.J.Hemink, T.Tanaka, M.Momodomi, K.Sakui, and R.Shirota, “A 1.13mm² memory cell technology for reliable 3.3V 64M NAND EEPROMs,” in Extended Abstracts of SSDM, pp.446-448, Aug.1993.

[28] M.Momodomi, R.Shirota, K.Sakui, T.Endoh, and F.Masuoka, “Trend of NAND Flash memory and future development,” in International Workshop on Advanced LSI’s, pp.219-225, July 1995.

[29] K.Sakui, T.Tanaka, H.Nakamura, M.Momodomi, T.Endoh, R.Shirota, S.Watanabe, K.Ohuchi, and F.Masuoka, “A shielded bitline sensing technology for a high-density and low-voltage NAND EEPROM design,” in International Workshop on Advanced LSI’s, pp.226-232, July 1995.

[30] K.Sakui, Y.Itoh, R.Shirota, Y.Iwata, S.Aritome, T.Tanaka, K.Imamiya, J.Kishida, M.Momodomi, and J.Miyamoto, “Invited Paper: NAND Flash memory technology and future direction,” in IEEE 1997 NVSMW, pp.1-34, Feb. 1997.

[31] F.Arai, T.Maruyama and R.Shirota, “Extended Data Retention Process Tcdhnology for Highly Reliable Flash EEPROMs of 10⁶ to 10⁷ W/E Cycles”, in IEEE IRPS 1998, pp.378-382, April 1998.

[32] R.Shirota, “Invited paper: A Review of 256Mbit NAND Flash Memories and NAND Flash Future Trend.” in Non-Volatile Semiconductor Memory Workshop, pp.22-32, Feb.2000.

[33] R.Shirota, “Test and repair of non-volatile commodity and embedded memories (NAND flash memory) “ in IEEE test Conference, pp.1221,Oct. 2002

[34] R.Shirota, “Invited paper:Future Trends in NAND-Type Flash Memory,” in Extended Abstracts of SSDM, pp.250-251, Aug.2004.

[35] R.Shirota, “Review of NAND Flash reliability,” in IEEE IRPS Tutorial notes, No.223, April 2005.

[36] R.Shirota, “NAND Flash Scaling and Technology Development” in Japan Semiconductor Technology Forum”, Jan. 2006.

[37] R.Shirota, “ Roadmap of the Flash Memory”, IEEE International Workshop on Digital Object Identifier in Memory Technology, Design, and Testing, MTDT, pp: xii – xii, Jun. 2006

[38] BREAKTHROUGH---Memory of the Future, The JAPAN, Journal, August, 2006

[39] R.Shirota, “Scaling trend of Flash memory for File storage”, in Memory, Tech, Design, Testing Workshop, pp.16, 2007.

[40] R.Shirota, “Review of recent development of high density Flash memory”, in New Non-Volatile Memory Workshop at ITRI, session B1, Nov. 2008.

[41] Hsin-Heng Wang, Chiu-Tsung Huang, Shin-Hsien Chen, Kuo, R, Sophia Liu, Ling-Kuey Yang, Houng-Chi Wei, Pittikoun, S., R.Shirota, Chin-chen Cho, ”A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory”, in VLSI-TSA International Symposium, pp.87 – 88, 2008.

[42] R.Shirota, “Review of Recent Flash Memory Development”, in Symposium on Nano Device Technology, Session 1.2, Apr. 2010.

[43] C.H.Liu, Y.M.Lin, R.Shirota, H.C.Wei, L.T.Kuo, C.Han.Liu, S.H.Chen, H.P.Wang, Y.Sakamoto, S.Pittikoun, “Self-Aligned Trench Isolation Recess Effect on Cell Performance and Reliability of 42nm NAND Flash Memory”, in VLSI-TSA, Session 3.1, Apr. 2010.

Ø      IEDM

[1]  F.Masuoka, M.Momodomi, Y.Iwata, and R.Shirora, “New Ultra High Density EPROM and Flash EEPROM with NAND Structured Cell,” in IEDM Tech. Dig., pp.552-555, Dec. 1987.

[2]  M.Momodomi, R.Kirisawa, R.Nakayama, S.Aritome, T.Endoh, Y.Itoh, Y.Iwata, H.Oodaira, T.Tanaka, M.Chiba, R.Shirota, and F.Masuoka, “New device technologies for 5V-only 4Mb EE-PROM with NAND structure cell,” in IEDM Tech. Dig., pp.412-415, Dec. 1988.

[3]  R.Shirota, T.Endo, M.Momodomi, R.Nakayama, S.Inoue, R.Kirisawa, and F.Masuoka, “An accurate model of subbreakdown due to Band-to-Band tunneling and its application,” in IEDM Tech. Dig., pp.26-29, Dec. 1988.

[4]  T.Endo, R.Shirota, Y.Tanaka, R.Nakayama, R.Kirisawa, S.Aritome, and F.Masuoka, “New design technology for EEPROM memory cells with 10 million write/erase cycling endurance,” in IEDM Tech. Dig., pp.599-602, Dec. 1989.

[5]  R.Shirota, R.Nakayama, R.Kirisawa, M.Momodomi, K.Sakui, Y.Itoh, S.Aritome, T.Endoh, F.Hatori, and F.Masuoka, "A 2.3 m2 Memory Cell Structure for 16 Mb NAND EEPROM’s," in IEDM Tech. Dig., pp. 103-106, Dec. 1990.

[6]  S.Aritome, R.Shirota, R.Kirisawa, T.Endoh, R.Nakayama, K.Sakui, and F.Masuoka, “A reliable bi-polarity write/erase technology in Flash EEPROMs,” in IEDM Tech. Dig., pp.111-114, Dec. 1990.

[7]  R.Shirota, T.Yamaguchi, “A New Analytical Model for low Voltage Hot Electron Taking Auger Recombination as well as phonon Scattering Process into Account,” in IEDM Tech. Dig. pp.123-126. 1991.

[8]  S.Aritome, S.Satoh, T.Maruyama, H.Watanabe, S.Shuto, G.J.Hemink, R.Shirota, S.Watanabe, and F.Masuoka, "A 0.67m2 Self-Aligned Shallow Trench Isolation Cell (SA-STI-Cell) for 3V-only 256Mbit NAND EEPROM’s," in IEDM Tech. Dig., pp. 61-64, Dec. 1994.

[9]  S.Aritome, Y.Takeuchi, S.Sato, H.Watanabe, K.Shimizu, G.J.Hemink, and R.Shirota, “A novel side-wall transfer-transistor cell (SWATT cell) for multi-level NAND EEPROM’s,” in IEDM Tech. Dig., pp.275-278, Dec. 1995.

[10] S.Satoh, H.Hagiwara, T.Tanzawa, K.Takeuchi, and R.Shirota, "A Novel Isolation-Scaling Technology for NAND EEPROMs with the Minimized Program Disturbance," in IEDM Tech. Dig., pp. 291-294, Dec. 1997.

[11] A.Goda, W.Moriyama, H.Hazama, H.Iizuka, K.Shimizu, S.Aritome and R.Shirota, “A Novel Surface-Oxidized Barrier-SiN Cell Technology to improve Endurance and Read-Disturb Characteristics for Gigabit NAND Flash Memories.” In IEDM Tech. Dig., pp.771-774, Dec. 2000.

[12] F.Arai, S.Satoh, T.Yaegashi, E.Kamiya, Y.Matunaga, Y.Takeuchi, H.Kamata, A.Shimizu, N.Ohtani, N.Kai, S.Takahashi, W.Moriyama, K.Kugimiya, S.Miyazaki, T.Hirose, H.Meguro, K.Hatakeyama, K.Shimizu, R.Shiorta, “High Density(4.4F²) NAND Flash technology Using Super-Shallow Channel Profile(SSCP) engineering.” In IEDM tech. Dig., pp775-778, Dec. 2000. 

 

Ø      ISSCC

[13] Y.Itoh, M.Momodomi, R.Shirota, Y.Iwata, R.Nakayama, R.Kirisawa, T.Tanaka, K.Toita, S.Inoue, and F.Masuoka, “An Experimental 4Mb CMOS EEPROM with a NAND Structured Cell,” in ISSCC Dig. Tech. Papers, pp.134-135, Feb. 1989.

[14] K.Imamiya, Y.Sugiura, H.Nakamura, T.Himeno, K.Takeuchi, T.Ikehashi, K.Kanda, K.Hosono, R.Shirota, S.Aritome, K.Shimizu, K.Hatakeyama, and K.Sakui, “A 130mm2 256Mb NAND Flash with Shallow Trench Isolation Technology,” in ISSCC Dig. Tech. Papers, pp.112-113, Feb. 1999.

[15] H.Nakamura, K.Imamiya, T.Himeno, T.Yamamura, T.Ikehashi, K.Takeuchi, M. Kanda, K.Hosono, T.Futatsuyama, K.Kawai, R.Shirota, N.Arai, F.Arai, K.Hatakeyama, H.Hazama, M.Saito, H.Meguro, K.Conley, K.Quader, Chen.Jian , “A 125mm² 1Gb NAND flash memory with 10MB/s program throughput “ in ISSCC, Dig. Tech. Parers, pp.82-411, Feb. 2002

 

Ø      VLSI technology

[16] R.Shirota, Y.Itoh, R.Nakayama, M.Momodomi, S.Inoue, R.Kirisawa, Y.Iwata, M.Chiba, and F.Masuoka, “A new NAND cell for ultra high density 5V only EEPROMs,” in Symp. VLSI Technology Dig. Tech. Papers, pp.33-34, June 1988.

[17] R.Kirisawa, S.Aritome, R.Nakayama, T.Endoh, R.Shirota, and F.Masuoka, "A NAND Structured Cell with a New Programming Technology for High Reliable 5 V-Only Flash EEPROM," in Symp. VLSI Technology Dig. Tech. Papers, pp.129-130, June 1990.

[18] H.Watanabe, S.Aritome, G.J.Hemink, T.Maruyama, R.Shirota, “Sacling of tunnel oxide thickness for Flash EEPROMs Realizing Stress-Induced Leakage Current Reduction”, in Symp. VLSI Technology Dig. Tech. Papers, pp.47-45, June, 1994.

[19] H.G.Hemink, T.Tanaka, T.Endoh, S.Aritome, and R.Shirota, “Fast and accurate programming method for multilevel NAND flash EEPROM’s,” in Symp. VLSI Technology Dig. Tech. Papers, pp.129-130, June 1995.

[20] S.Satoh, K.Shimizu, T.Tanaka, F.Arai, S.Aritome, and R.Shirota, “A novel Channel Boost Capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4Gbit NAND Flash memories,” in Symp. VLSI Technologies Dig. Tech. Papers, pp.108-109, June 1998.

[21] M.Ichige, Y.Takeuchi, K.Sugimae, A.Sato, M.Matsui, T.Kamigaki, H.Kutsukake, Y.Ishibashi, M.Saito, S.Mori, H.Meguro, S.Miyazaki, T.Miwa, S.Takahashi, T.Iguchi, N.Kawai, S.Tamon, N.Arai, H.Kamata, T.Minami, H.Iizuka, M.Higashitani, T.Pham, G.Hemink, M.Momodomi and R.Shirota, “A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND Flash EEPROMs,” in Symp. VLSI technologies Dig. Tech. Papers, pp.89-90, June 2003.

 

Ø      VLSI Circuits

[22] T.Tanaka, M.Momodomi, Y.Iwata, Y.Tanaka, H.Oodaira, Y.Itoh, R.Shirota, K.Ohuchi, and F.Masuoka, “A 4-Mbit NAND-EEPROM with tight programmed Vt distribution,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.105-106, June 1990.

[23] T.Tanaka, Y.Tanaka, H.Nakamura, H.Oodaira, S.Aritome, R.Shirota, and F.Masuoka, “A Quick Intelligent Page-Programming Architecture 3V-Only NAND- EEPROMs,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.20-21, June 1992.

[24] T.Tanzawa, T.Tanaka, K.Takeuchi, R.Shirota, S.Aritome, H.Watanabe, G.Hemink, K.Shimizu, S.Sato, Y.Takeuchi, and K.Ohuchi, “A compact on-chip ECC for low cost Flash memories,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.59-60, June 1996.

 

Ø      Other Conferences

[25] M.Momodomi, Y.Iwata, T.Tanaka, Y.Ithoh, R.Shirota, F.Masuoka, “A high density NAND EEPROM with Block-page Programming for Micorcomputer Applications”, in IEEE CICC, pp.10.1.1-4, May, 1989.

 

[26] S.Aritome, R.Kirisawa, T.Endoh, N.Nakayama, R.Shirota, K.Sakui, K.Ohuchi, and F.Masuoka, “Extended Data Retention Characteristics after more than 104 Write and Erase Cycles in EEPROM’s,” in IEEE IRPS 1990, pp.259-264, 1990.

[27] S.Aritome, K.Hatakeyama, T.Endoh, T.Yamaguchi, S.Shuto, H.Iizuka, T.Maruyama, H.Watanabe, G.J.Hemink, T.Tanaka, M.Momodomi, K.Sakui, and R.Shirota, “A 1.13mm² memory cell technology for reliable 3.3V 64M NAND EEPROMs,” in Extended Abstracts of SSDM, pp.446-448, Aug.1993.

[28] M.Momodomi, R.Shirota, K.Sakui, T.Endoh, and F.Masuoka, “Trend of NAND Flash memory and future development,” in International Workshop on Advanced LSI’s, pp.219-225, July 1995.

[29] K.Sakui, T.Tanaka, H.Nakamura, M.Momodomi, T.Endoh, R.Shirota, S.Watanabe, K.Ohuchi, and F.Masuoka, “A shielded bitline sensing technology for a high-density and low-voltage NAND EEPROM design,” in International Workshop on Advanced LSI’s, pp.226-232, July 1995.

[30] K.Sakui, Y.Itoh, R.Shirota, Y.Iwata, S.Aritome, T.Tanaka, K.Imamiya, J.Kishida, M.Momodomi, and J.Miyamoto, “Invited Paper: NAND Flash memory technology and future direction,” in IEEE 1997 NVSMW, pp.1-34, Feb. 1997.

[31] F.Arai, T.Maruyama and R.Shirota, “Extended Data Retention Process Tcdhnology for Highly Reliable Flash EEPROMs of 10⁶ to 10⁷ W/E Cycles”, in IEEE IRPS 1998, pp.378-382, April 1998.

[32] R.Shirota, “Invited paper: A Review of 256Mbit NAND Flash Memories and NAND Flash Future Trend.” in Non-Volatile Semiconductor Memory Workshop, pp.22-32, Feb.2000.

[33] R.Shirota, “Test and repair of non-volatile commodity and embedded memories (NAND flash memory) “ in IEEE test Conference, pp.1221,Oct. 2002

[34] R.Shirota, “Invited paper:Future Trends in NAND-Type Flash Memory,” in Extended Abstracts of SSDM, pp.250-251, Aug.2004.

[35] R.Shirota, “Review of NAND Flash reliability,” in IEEE IRPS Tutorial notes, No.223, April 2005.

[36] R.Shirota, “NAND Flash Scaling and Technology Development” in Japan Semiconductor Technology Forum”, Jan. 2006.

[37] R.Shirota, “ Roadmap of the Flash Memory”, IEEE International Workshop on Digital Object Identifier in Memory Technology, Design, and Testing, MTDT, pp: xii – xii, Jun. 2006

[38] BREAKTHROUGH---Memory of the Future, The JAPAN, Journal, August, 2006

[39] R.Shirota, “Scaling trend of Flash memory for File storage”, in Memory, Tech, Design, Testing Workshop, pp.16, 2007.

[40] R.Shirota, “Review of recent development of high density Flash memory”, in New Non-Volatile Memory Workshop at ITRI, session B1, Nov. 2008.

[41] Hsin-Heng Wang, Chiu-Tsung Huang, Shin-Hsien Chen, Kuo, R, Sophia Liu, Ling-Kuey Yang, Houng-Chi Wei, Pittikoun, S., R.Shirota, Chin-chen Cho, ”A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory”, in VLSI-TSA International Symposium, pp.87 – 88, 2008.

[42] R.Shirota, “Review of Recent Flash Memory Development”, in Symposium on Nano Device Technology, Session 1.2, Apr. 2010.

[43] C.H.Liu, Y.M.Lin, R.Shirota, H.C.Wei, L.T.Kuo, C.Han.Liu, S.H.Chen, H.P.Wang, Y.Sakamoto, S.Pittikoun, “Self-Aligned Trench Isolation Recess Effect on Cell Performance and Reliability of 42nm NAND Flash Memory”, in VLSI-TSA, Session 3.1, Apr. 2010.

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73, Fabrication method of a nonvolatile semiconductor memory
US Pat. 7141474 - Filed Dec 10, 2004

 

Ø      Registered Japanese patent list

1. 特许4271223 半导体集积回路装置

2. 特许4284300 半导体记忆装置

3. 特许4105188 不挥発性半导体记忆装置およびそのデータ消去方法

4. 特许4331053 半导体记忆装置

5. 特许4153856 不挥発性半导体记忆装置

6. 特许4005000半导体记忆装置及びデータ书き込み方法

7. 特许3762385 不挥発性半导体记忆装置

8. 特许3927156 不挥発性半导体记忆装置

9. 特许3762416 不挥発性半导体记忆装置

10. 特许3914142 不挥発性半导体记忆装置及びその制造方法

11. 特许3857640 半导体记忆装置

12. 特许3883534 不挥発性半导体记忆装置、キャッシュメモリシステム、半导体记忆装置、および半导体记忆システム

13. 特许3906190 フラッシュメモリシステムおよびエラー订正方法

14. 特许4068519 有効期限付き机能利用装置

15. 特许3906177 不挥発性半导体记忆装置

16. 特许4004809 半导体装置及びその动作方法

17. 特许3749891 不挥発性メモリおよび记忆システム

18. 特许4034594 不挥発性半导体メモリ

19. 特许4266089 半导体记忆装置及びその制造方法

20. 特许4109845 不挥発性半导体记忆装置の制造方法

21. 特许4309078 半导体装置及びその制造方法

22. 特许3957985 不挥発性半导体记忆装置

23. 特许3600562 半导体记忆装置

24. 特许4128737 半导体装置及び半导体记忆装置の制造方法

25. 特许4008651 半导体装置とその制造方法

26. 特许3600561 误り订正検出回路と半导体记忆装置

27. 特许4064611 半导体装置及びその制造方法

28. 特许4131900 半导体记忆装置及びその制造方法

29. 特许4313941 半导体记忆装置

30. 特许3727864 不挥発性半导体记忆装置

31. 特许3474857 メモリセルのメモリ状态変更方法、不挥発性半导体メモリ装置およびフラッシュメモリシステム

32. 特许3495337 キャッシュメモリシステム、半导体记忆装置、不挥発性半导体记忆装置、半导体记忆システムおよびメモリベリファイ回路

33. 特许3474856 不挥発性半导体记忆装置

34. 特许4031167 不挥発性半导体记忆装置

35. 特许3878374 不挥発性半导体记忆装置

36. 特许4047500 半导体装置及びその制造方法

37. 特许4246831 半导体集积回路装置

38. 特许3540633 半导体装置の制造方法

39. 特许3725708 半导体装置

40. 特许3786513 不挥発性半导体记忆装置

41. 特许4330670 不挥発性半导体记忆装置

42. 特许3557078 不挥発性半导体记忆装置

43. 特许3382151 不挥発性半导体记忆装置

44. 特许3576686 不挥発性半导体记忆装置

45. 特许3207354 不挥発性半导体记忆装置

46. 特许3176019 不挥発性半导体记忆部を含む记忆システム

47. 特许3272903 误り订正検出回路と半导体记忆装置

48. 特许3383429 不挥発性半导体记忆装置およびデータ书き込み方法

49. 特许3383427 不挥発性半导体装置

50. 特许3181478 不挥発性半导体记忆装置

51. 特许3405567 不挥発性半导体记忆装置

52. 特许3207592 不挥発性半导体记忆装置

53. 特许3152756 不挥発性半导体记忆装置

54. 特许2647321 不挥発性半导体记忆装置及びこれを用いた记忆システム

55. 特许3170038 不挥発性半导体记忆装置

56. 特许3501405 不挥発性半导体装置の制造方法

57. 特许3162472 不挥発性半导体记忆装置

58. 特许3228996 不挥発性半导体记忆装置

59. 特许3226589 不挥発性半导体记忆装置およびその制造方法

60. 特许3152720 不挥発性半导体记忆装置

61. 特许3210373 不挥発性半导体记忆装置

62. 特许3210355 不挥発性半导体记忆装置

63. 特许3029297 半导体记忆装置

64. 特许3004043 不挥発性半导体メモリ装置

65. 特许3104978 不挥発性半导体记忆装置の制御方法

66. 特许3099887 不挥発性半导体记忆装置

67. 特许2809802 不挥発性半导体记忆装置

68. 特许2818202 不挥発性半导体记忆装置

69. 特许2944104 不挥発性半导体记忆装置

70. 特许2885413 不挥発性半导体メモリ装置

71. 特许2885412 不挥発性半导体メモリ装置

72. 特许2904498 不挥発性半导体メモリ装置およびその制造方法

73. 特许2804066 不挥発性半导体メモリ装置

74. 特许2772020 ＭＯＳ型半导体装置

75. 特许2695881 ＭＯＳ型半导体装置

76. 特许2957586 不挥発性メモリセルの制造方法

77. 特许2718716 不挥発性半导体メモリ装置およびそのデータ书替え方法

78. 特许2732601 不挥発性半导体メモリ装置

79. 特许2667444 不挥発性半导体记忆装置

80. 特许2818190 不挥発性半导体记忆装置およびその制造方法

81. 特许2726432 不挥発性半导体メモリ装置

82. 特许2723247 不挥発性半导体メモリ装置

83. 特许2724150 不挥発性半导体メモリ装置

84. 特许2685770 不挥発性半导体记忆装置

85. 特许2635638 不挥発性半导体メモリ装置の制造方法

86. 特许2573271 不挥発性半导体メモリ装置

87. 特许2618946 不挥発性半导体メモリ装置の制造方法

88. 特许2637127 不挥発性半导体メモリ装置

89. 特许2635630 不挥発性半导体メモリ装置

90. 特许2786629 不挥発性半导体メモリ装置

91. 特许2647101 不挥発性半导体メモリ装置

92. 特许2677565 不挥発性半导体メモリ装置及びその制御方法

93. 特许1863951 半导体装置の制造プロセスにおけるチャージアップ量测定方法

94. 特许2618898 记忆装置

95. 特许2760983 不挥発性半导体记忆装置及びその制造方法